The present invention relates in general to interconnect structures for integrated circuits on a semiconductor chip wherein patterned interfaces are applied to or formed in the interconnects to alter and optimize the stress state which is imparted to the interconnects from adjacent insulator or passivation layers.
The metallization systems used in integrated circuits on a semiconductor chip often include several layers of narrow and thin metal interconnects which are separated by insulator or passivation layers and are connected by vias through the same. More particularly, the narrow and thin metal interconnects are deposited on an insulator layer that covers the semiconductor chip and are connected to the underlying devices in the chip through holes or vias drilled through the insulator layer. The interconnects are covered by a passivation layer for corrosion and electromigration resistance.
Good adhesion between the metal interconnects and their surrounding passivation and insulator layers is important to produce good thermal contact in order to dissipate the heat generated in the interconnects when a high current is passed therethrough. The adhesion is also important to facilitate the fabrication of the interconnect structure.
To improve the reliability of aluminum based interconnects, a refractory metal underlayer, top layer or both have been used. The refractory metals are typically tungsten, titanium or their alloys. A thin titanium layer can also be sandwiched in the aluminum based interconnect. These refractory metal layers maintain electrical continuity even when the aluminum alloy layer is severed by stress migration or electromigration damage.
Stress migration produces two forms of damages. When large tensile stresses are present in the metal interconnects, the formation of stress-induced voids will occur. Sufficiently large voids will increase the line resistance or sever the interconnect. On the other hand, when large compressive stresses are present, the formation of stress induced hillocks, which are protrusions growing out of the interconnect, will occur. Sufficiently large hillocks will fracture the passivation layer thus producing shorts between interconnects and exposing the interconnects to the external environment.
Whether the state of stress in an interconnect is compressive or tensile depends on the passivation temperature, the post passivation heat treatment or processing temperatures and the extent of stress relaxation during a temperature hold. In general, if the passivation temperature is higher or equal to the maximum temperature during a post passivation temperature excursion, the state of stress in the interconnect will be mainly tensile in the absence of substantial stress relaxation.
If stress-migration induced voids are present in an interconnect, although they may not be large enough by themselves to increase the interconnect resistance or sever the interconnect, they will grow and migrate under an applied high electrical current. Void coalescence will occur due to void velocity distribution because the migration velocity of a void varies depending on its size. Void coalescence will result also from other causes such as from variations in electrical current density caused by changes in interconnect geometry. Such void coalescence will increase the interconnect resistance and sever the interconnect in much the same way as stress-migration induced void growth. This form of electromigration damage is thus stress migration related and is considered to be an important electromigration damage process in passivated interconnects. If, however, stress-migration induced voiding is significantly reduced, the electromigration resistance of passivated interconnects will improve.
Strong passivation and insulator layers are necessary to limit electromigration damage produced by high electrical current driven atomic transport. The reason for this is that if the passivation and insulator layers surrounding the interconnect are strong, it is possible to build up a back stress due to electrical current driven atomic transport in the interconnect which will limit continued atomic transport. At the same time, if a metal alloy interconnect is well adhered to the strong passivation and insulator layers to meet the thermal resistance and processing requirements, a strong triaxial tensile stress state will be created in the interconnect when it contracts more than the surrounding layers. For example, the coefficient of thermal expansion of aluminum is significantly larger than that of silicon oxide or silicon nitride which is used to make the surrounding layers so that if the interconnect is made from an aluminum alloy, it will always contract or expand more than the latter during a temperature cycle. The resulting high triaxial tensile stresses are believed to be the cause of stress-migration induced voiding.